Praveen Akula

About Praveen Akula

STA and physical design engineer with experience in- Complete RTL to GDS flow at…

Experience

1. Staff Engineer

   高通

   Jan 2025 — Present · IN

Education

• SS Junior College

  Inter, MPC

  2004 — 2006

• SR ENGINEERING COLLEGE

  Bachelor of Technology (B.Tech.), Electronics and Communications Engineering

  2006 — 2010

• VNR VJIET

  Master of Technology (M.Tech.), VLSI SYSTEM DESIGN

  2010 — 2012

• Z.P.S.S, Damera

  SSC

  2000 — 2004

Skills

• Fpga
• Asic
• Cadence Virtuoso
• Very-Large-Scale Integration (Vlsi)
• Physical Design
• Cadence
• Core Java
• C
• Verilog
• Modelsim
• Vlsi
• Physical Verification
• Systemverilog
• Clock Tree Synthesis
• Functional Verification
• Verilog Hdl
• Cadence Ets
• Low-Power Design
• Floorplanning
• System Verilog
• Tcl Script
• Timing Closure
• Dft
• Synopsys Vcs
• Xilinx Ise
• Soc
• Logic Synthesis
• Tcl
• Cmos
• Cadence Soc Encounter
• Static Timing Analysis
• Cadence Rtl Compiler
• Synopsys Tools