Pravallika Aluri
Senior Design Verification Engineer @Quest Global
Signup · Get unlimited contacts
WORK HISTORY
Senior Design Verification Engineer @Quest Global
Hyderabad, IN
EDUCATION
Ragiv Gandhi University of knowledge and technologies,Nuzvid
Bachelor of Technology - BTech, Electronics and communication engineering
RAJIV GANDHI UNIVERSITY OF KNOWLEDGE TECHNOLOGIES, NUZVID
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering
ABOUT PRAVALLIKA ALURI
Design Verification Engineer with 3.5+ years of hands-on experience in digital at IP, subsystem, and ASIC levels. Strong expertise in SystemVerilog, UVM, SVA, coverage-driven verification, scoreboard development, debug, and regression automation. Proven experience verifying high-speed data paths and bus-based architectures using AXI/APB/AHB, SPI, and Ethernet. Adept at collaborating with design teams to achieve first-pass verification closure for complex ASIC’sCore Skills • Languages & Methodologies: SystemVerilog (UVM, SVA), Verilog, VHDL • Protocols & Interfaces: AXI, APB, SPI, Ethernet (10G/1G PCS-PMA + MAC/TEMAC SGMII) • Tools & Simulators: Synopsys VCS, Mentor QuestaSim, Verdi, DVE, Vivado • Scripting & Automation: Makefile, Perl • Verification Expertise: Testbench Architecture, Constrained Random Testing, Functional & Code Coverage, Scoreboard Development, Assertions (SVA), Pipeline Verification, GLS Verification • Additional Skills: Git, Regression Management, Debug & Failure Analysis
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.