Pratish Kumar

About Pratish Kumar

Exposure to Functional Verification, RTL design, Gate Level Simulation, Power Estimation, Modeling designs in C for verification and for driver development.2. Programming skills - E, System Verilog, C, Verilog, Perl, Python, CPP, SystemC, shell scripts, make. Version control - git, clearcase, SVN.3. Exposure to the Cache and Processor Memory Subsystem Architecture, Hardware Accelerators for the Display Processing Algorithms.4. Mentoring teammates, interns and sub-contractors simultaneously.5. Intra company communication – support to the system level team and software team which takes the IP.6. Piloted VMM based verification methodology, UVM e based verification methodology with CtoS flow for the Display related IP and deployed the methodology across the team.7. Drove a new methodology within the team for quicker coverage closure and deployed the same across several modules.8. Developed and delivered an integrated C functional model for Virtual Platform team to enable driver development for the display controller IP and drove a new methodology for Hardware -Software Co-Verification for Display Sub System using Virtual Platform.9. Successfully lead a team of 3 for DV activities of two Display Sub System derivatives.10. Top level verification of A73 via single thread random instruction generator.11. Random Instruction Generator Lead for A75 with a team of 3.12. Detailed investigation and verification plan creation for ARM v9 architecture.13. Plan creation for Cortex A715 top level verification. Test bench setup, continuous integration setup and process for quicker turnaround.14. Team creation and technical mentorship for verification of multi CPU coherency verification on FPGA. Cross team memory sub system mentorship.15. Technical mentorship for memory ordering tool deployment across team and cloud deployment for verification payloads16. Automation using Machine Readable Specifications for verification collateral.17. Co-lead for unit level verification team for DSU-110 and upcoming revisions.

Experience

1. Principal Engineer

   Arm

   Apr 2014 — Present

Education

• National Institute of Technology, Tiruchirappalli

  B TECH

  2003 — 2007

Skills

• Soc
• Debugging
• Functional Verification
• Asic
• Verilog
• Ic
• Vlsi
• Eda
• Rtl Design
• Static Timing Analysis