Pratik D.

Senior Principal Emulation Engineer @Cadence

Portland, OR, US
MOBILE NUMBERS
+91 *********19

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WORK HISTORY

Jul 2025 — Present

Senior Principal Emulation Engineer @Cadence

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US

EDUCATION

2005 — 2009

University of Mumbai

Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering

2009 — 2011

San José State University

M.S, Electrical Engineering (VLSI)

SKILLS

UnixUvmQuartusOperating SystemsFormal VerificationVlsiAnalogComputer ArchitectureSpectreVhdlVisioLinuxModelsimHtmlXilinxMs Office SuiteFpgaAsicC++Logic AnalyzerVery-Large-Scale Integration (Vlsi)CSimulinkSpectrum AnalyzerRtl DesignIntegrated Circuit DesignMicroprocessorsMultisimAssemblyCadence VirtuosoWindowsField-Programmable Gate Arrays (Fpga)MatlabVcsDigital DesignVisual BasicVerilogAlgorithmsPerlEmbedded Systems

ABOUT PRATIK D.

Emulation Engineer with 13+ years of experience in hardware validation and FPGA prototyping across Microsoft, Intel, Qualcomm, and Texas Instruments. Specialized in building scalable emulation infrastructures, optimizing flows on Zebu and Palladium platforms, and deploying AI-driven automation to accelerate pre-silicon testing. Proven track record in architecting multi-FPGA systems, enabling early firmware bring-up, and solving complex system-level challenges through cross-functional collaboration.

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