Pratibha Munnangi
Asic Physical Design Engineer Intern @Alphawave Semi
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WORK HISTORY
Asic Physical Design Engineer Intern @Alphawave Semi
Explored and implemented different types of power recipes on die-to-die partitions to improve power efficiency.• Communicated power optimization updates and performed power failure checks for 8 partitions, providing solutions to partitionowners.• Implemented Power ECOs like swap, size, remove buffer after investigating power ECO change list.• Achieved ~12mW of total power per instance count by implementing machine learning algorithms (DSO.ai) at end of the project.
EDUCATION
RVR & JC College of Engineering
Bachelor of Technology - BTech
Portland State University
Master of Science - MS
SKILLS
ABOUT PRATIBHA MUNNANGI
ASIC Physical Design Engineer @Alphawavesemi | Actively seeking full time opportunities in Physical Design, Digital Design | Alumna @PSU
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