Prathyusha Madapalli
Senior VLSI Physical Design & PDK Engineer
- Role
- Pdk Engineer at Intel
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Pdk Engineer
Mar 2020 — Present
Education
Godavari Institute of Engineering & Technology (GIET)
Master of Technology (M.Tech.), VLSI & Embedded Systems
2014 — 2016
SRI PRAKASH COLEGE OF TECHNOLOGY
Bachelor of Technology (BTech), Electrical and Electronics Engineering
2010 — 2014
Skills
- Cadence Innovus
- Pspice
- Clock Tree Synthesis
- Microsoft Office
- Tcl
- Verilog Hdl
- C
- Matlab
- Cadence Encounter
- Vhdl
- Physical Design Flow
- Microcontrollers
- Electronics
- Sta
- Placement
- Microsoft Excel
- Perl
- Microsoft Powerpoint
- Management
- Timing Analysis
- Xilinx
- Microsoft Word
- Programming
- Place & Route
- Windows
- Congestion Analysis
- Star Rc
- Verilog
- Powerpoint
- Digital Concepts
- Synopsys Primetime
- Floorplanning
- Routing
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