Pratheep A Nair
Physical Design Expert on Chip Integration
- Role
- Master Engineer at Broadcom
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Pratheep A Nair
Techno-managerial professional with 25+ years of industry experience as a hands-on IC Design Manager/Engineer Currently working as Senior Director at Intel responsible for leading a team for high-power computing chips Hallmark career dotted with impactful roles in: o Backend Design using Innovus, ICC, and Atop o Full Chip Physical Verification using Calibre tools o Full Chip PNR and Integration o Flip Chip Implementation o Dynamic IR Drop Analysis using Ansys Redhawk Effective leader with the competency in spearheading technical teams and mentoring various teams in full chip integration, IP development, and CAD flow development
Experience
Master Engineer
Dec 2023 — Present · IN
Chip design
Education
Cochin University of Science and Technology
BTech, Electronics
1990 — 1994
Indian Institute of Technology, Bombay
M.Tech, MicroElectronics
1997 — 1999
Skills
- Debugging
- Static Timing Analysis
- Place & Route
- Vlsi
- Floorplanning
- Die to Package Handoff
- Eda
- Timing Closure
- Semiconductors
- Ir Drop Analysis
- Padring Development
- Asic
- Full Chip Integration
- Logic Synthesis
- System on a Chip (Soc)
- Ic
- Physical Design
- Power Ic
- Verilog
- Soc
- Physical Verification
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