Pratheek Jain

About Pratheek Jain

Over 3+ years of experience in SoC design verification, specializing in UVM-based methodologies and complex SoC environments. Strong experience in Verilog, SystemVerilog, and UVM-based verification Solid understanding of the ASIC verification flow — including test planning, testcase development, and testbench architecture Hands-on experience in IP-level and SoC-level verification, with strong debugging skills Coverage-driven functional verification proficiency in block-level, subsystem and system-level verification Experience in Gate-Level Simulation (GLS) and SDF-annotated verification Knowledgeable in protocols: APB, AXI, AXI-Lite, UART, I2C, SD 6.0 UHS-I, eMMC 5.1 Skilled in developing testbenches and automating verification flows using Python Familiar with industry-standard simulation and debug tools: VCS, Verdi Experience in writing SoC-level tests using C++ Strong ability to identify and debug complex SoC-level verification issuesCommitted to delivering high-quality verification, driving coverage closure, and ensuring first-time-right silicon through systematic verification, robust debugging, and continuous improvement.

Experience

1. Engineer Ii

   SEMIFIVE

   Apr 2025 — Present

Education

• SDM INSTITUTE OF TECHNOLOGY (SDMIT), UJIRE

  Bachelor of Engineering - BE, Electrical and Electronics Engineering

  2016 — 2020