Prathamesh Chodankar

About Prathamesh Chodankar

Myself Prathamesh Chodankar, I have M.Tech Degree in VLSI Design from Vellore Institute of Technology(VIT) Vellore, Tamil Nadu, India and currently I am working in CPUSS RTL Design team at Intel, India with experience of ~8 years. In my total experience in Qualcomm & Intel, I have worked in both ARM & Intel Architectures to deliver high quality CPUSS RTL to SOC. over the time I have gained experience in IP/SubSystem integration and also IP development.I have micro-architected so far 3 ARM based CPUSS in Intel and they have been successfully verified. In Intel, as part of leading the CPUSS design team, I was managing 3 team members as well. thus I have gained management experience as well.Recently, I am leading the CCF(converged Coherent Fabric) IP development effort with 5 other colleagues for Intel\'s latest Server chip. Technical Skills :1) EDA TOOLS :Synopsys Spyglass, Cadence Jaspergold, Cadence DMV, Cadence NCLaunch, Cadence Virtuoso Spectre Circuit Simulator, RTL Compiler, SoC Encounter, Virtuoso Schematic Editor, Cadence Virtuoso Analog Design Environment.2) HARDWARE DESCRIPTION LANGUAGE: Verilog HDL.3) SCRIPTING LANGUAGE: Perl.4) SOFTWARE LANGUAGES: C, C++, MATLAB.5) DESIGN TOOLS : ModelSim 6.6d6) FPGA SYNTHESIS TOOLS : Xilinx ISE, ALTERA-Quartus II7) FPGA HARDWARE IMPLEMENTATION: Altera Cyclone II Design Kit.8) DEVICE MODELLING AND SIMULATION : Silvaco TCADAreas of Interest :1) RTL Design2) Automation using Perl Programming3) Verification and Testing using Verilog HDL.4) Static timing Analysis5) Physical Design.

Experience

1. Staff Engineer

   Qualcomm

   Mar 2023 — Present · Bengaluru, IN

   Next generation Nuvia/Arm core cpuss.

Education

• Vellore Institute of Technology

  Master of Technology (MTech), VLSI Design

  2013 — 2015

• University of Mumbai

  Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering

  2008 — 2012