Prateek Chopra

About Prateek Chopra

11+ years of experience in VLSI frontend RTL design Experience in VLSI industry since last 11+ years. Experience in microarchitecturedesign, VHDL/Verilog RTL coding, synthesis, simulation,timing closure, emulation and SystemVerilog. Worked on standard protocols like DDR, GigaChip Interface (GCI), 10GEMAC, MDIO, I2C, SPI,UART & LPC. Tool used: Questasim, Modelsim, Quartus II, Xilinx ISE & Vivado.

Experience

1. Staff Engineer

   Qualcomm

   Apr 2025 — Present · IN

Education

• Vidhya Vikas Institute of Engineering and Technology

  Bachelor of Engineering (BE), Electrical, Electronic and Communications Engineering Technology/Technician

  2007 — 2011

• Central Academy,Jodhpur

  class X th,XII th, mathematics,physics,chemistry

  1992 — 2007

Skills

• Vlsi
• Open Verification Methodology
• Xilinx
• Systemverilog
• Static Timing Analysis
• Rtl Design
• Very-Large-Scale Integration (Vlsi)
• Verilog
• Semiconductors
• Microcontrollers
• Cmos
• Vhdl
• Fpga
• Asic
• Ic
• Soc
• Integrated Circuit Design
• Electronics
• Digital Designs
• Field-Programmable Gate Arrays (Fpga)
• C++
• Logic Synthesis
• Modelsim
• I2c
• C