Prasoon A K
Senior R&D Engineer at Synopsys | RTL Design Expert | Gold Medalist – NIT Calicut | Verilog & SystemVerilog | VLSI Architect in Progress | STA | CDC | IP Development
- Role
- Senior Rtl Design Engineer at 新思科技股份有限公司
- Location
- Kannur, KL, IN
- LinkedIn followers
- 500 followers
About Prasoon A K
I\'m a Senior Research & Development Engineer at Synopsys with a strong foundation in RTL design, digital architecture, and advanced VLSI methodologies. With 3+ years of experience in the semiconductor industry, I specialize in delivering high-performance and power-efficient IPs, driving innovation across the design flow.My technical toolkit includes Verilog, SystemVerilog, Synthesis (DC), Static Timing Analysis, CDC, Linting (SpyGlass), Fishtail and hands-on experience with Synopsys EDA tools. I’ve contributed to critical projects ranging from high-speed IP integration to custom design flows with an emphasis on timing closure.
Experience
Senior Rtl Design Engineer
Jun 2022 — Present · Hyderabad, IN
Spearheaded RTL design projects utilizing SpyGlass for quality checks and CDC analysis, ensuring high design integrity. • Collaborated with cross-functional teams to resolve RDC issues, enhancing overall design efficiency. • Executed formal verification processes using Formality, leading to a 30% reduction in design errors prior to synthesis.
Education
College of Engineering Trivandrum
electronics and communication, Electrical, Electronics and Communications Engineering
2012 — 2016
National Institute of Technology Calicut
Master of Technology - MTech, VLSI
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