Prashant Singh
Senior Principal Design Engineer
- Role
- Senior Principal Engineer-serdes Analog Design at Qualcomm
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
About Prashant Singh
Experience Summary -18 Year+ experience in Analog and Mixed Signal Circuit Design…
Experience
Senior Principal Engineer-serdes Analog Design
Dec 2022 — Present · Bengaluru, IN
Multi standard SerDes (28Gbps: CEI-28G-VSR, CAUI4: 25Gbps, PCI-Express:16Gbps, SATA etc.TX/ RX : CML TX,3-TAP FFE/ 4-TAP DFE / AFE (TCOIL/ODT/CTLE/VGA) in 16nm Fin Fet, channel loss -16dB @14GHz-High Speed SerDes Circuit Design ( TX/RX/Clocking): 10Gbps ( USB3.2/DP) Combo PHY in 22nm FDSOI - Design Lead for SerDes RX (Low power <1pJ/bit): 4-TAP DFE / AFE ( CTLE/AGC/ODT) in 22nm FDSOI- Work with MATLAB system team to model SerDes block and functionality to achieve maximum co- relation (circuit vs Model) for statistical eye @BER e-12-Support AMS Modelling team for various functional model verification-Innovation : Filed 5 patents and discover key adaption scheme with minimum impact on key specs ( power/LSB-Dithering/VT Drift /Nyquist boost/Linearity/Noise/3-dB BW.etc.)
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