Prasanth Reddy Veeramreddy
Design Verification Engineer at Capgemini Engineering| #VLSI, Motivator, Learner
- Role
- Design Verification Engineer at Capgemini Engineering
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
About Prasanth Reddy Veeramreddy
1.Good understanding of ASIC Design flow 2.Experience in writing verification test bench in System Verilog and UVM. 3.Experience in Simulation,Code Coverage, Functional coverage and Assertion Based Verification. 4.Experience in using industry using EDA TOOLS For the front -end design and verification Technical Skills HDL: Verilog HVL: system Verilog Methodology: UVM EDA Tools: ModelSim, Xilinx ISE Protocols : AXI, AHB, APB
Experience
Design Verification Engineer
May 2022 — Present · Bengaluru, IN
Having knowledge on AMBA Protocol like AHB, AXI protocols.\\\\n2. Performing the regression of various blocks and debugging the failure test cases.
Education
Sri Saraswathi High school
10Th STANDARD
2011 — 2012
Audisankara Institute of Technology, Gudur, India
Diploma, Electronics and Communications Engineering
2012 — 2015
G. Pullla Reddy Engineering College (Autonomous), Kurnool, India.
Bachelor of Technology - BTech, Electronics and Communications Engineering
2015 — 2018
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