Prasanna Kumar Thadapaneni

About Prasanna Kumar Thadapaneni

Seasoned and results-driven VLSI Physical Design Engineer with over 14+ years of extensive experience in ASIC implementation across advanced technology nodes, including 90nm, 65nm, 45nm, 22FDX, 14nm, 5nm, and 4nm. Proven track record in executing end-to-end RTL-to-GDSII flows and ensuring successful timing closure and signoff.Hands-on expertise in full-chip floorplanning using a bottom-up approach, flow development, Fullchip/block-level/section-level place-and-route (PnR), and implementation to signoff including STA.Successfully led over 12+ complex SoC projects from full-chip floorplanning to block implementation phases, including project and resource planning.Collaborated with leading global semiconductor clients, delivering high-quality, high-performance designs under tight schedules.Experienced in managing teams ranging from 5 to 80+ engineers, providing both technical leadership and project direction.Strong project planning skills, with a deep sense of ownership and accountability to meet schedule milestones and design objectives- ASIC/SoC Implementation- Project Planning, Tracking and Execution- Team management skills- Customer relationship management- Ability to build teams and execute complex projects

Experience

1. Co-founder & Director

   Silicon Patterns

   Jan 2025 — Present · Hyderabad, IN

Education

• JNTUH College of Engineering Hyderabad

  Bachelor of Technology (B.Tech.), Electronics and Communications Engineering

  2006 — 2010

• Central Institute of Tool Design

  Special Diploma in, Advanced Digital and Physical Design

  2010 — 2011

Skills

• Asic
• Drc
• First Encounter
• Cadence Virtuoso
• Timing Closure
• Linux
• Vlsi
• Static Timing Analysis
• Lvs
• Perl
• Physical Verification
• Tcl
• Physical Design
• Synopsys Primetime
• Systemverilog
• Clock Tree Synthesis
• Timing
• Floorplanning
• Primetime
• Routing