Prasanna Bumb
R&D Engineer II at Avago Technologies
- Role
- R & d Engineer Ii at Avago Technologies
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Prasanna Bumb
TECHNICAL SKILLS Languages: Verilog, System Verilog, VHDL, C, Assembly (8051…
Experience
R & d Engineer Ii
May 2015 — Present
Education
K.B.P. Polytechnic. MSBTE University
Diploma in Engineering, Electronics and Communications Engineering
2005 — 2008
San José State University
Master of Science (MS), Electrical Engineering specializing in Digital VLSI
2012 — 2014
Savitribai Phule Pune University
Bachelor of Engineering (BE), Electronics and telecommunication engineering
2008 — 2011
Skills
- Linux
- Modelsim
- Proficient on Pc & Mac
- Assembly Language
- Xilinx
- Systemverilog
- Functional Verification
- Unix
- Static Timing Analysis
- Synopsys Tools
- Testing
- Asic
- Tcl
- Verilog
- Microsoft Office
- Vlsi
- Altera Quartus
- Computer Architecture
- Rtl Design
- Turbo C
- Vhdl
- Shell Scripting
- Perl
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