Prasad Bharade

About Prasad Bharade

7+ years of experience in SoC/ASIC Design. Experience in, • Sglint and CDC checks using Synopsys SpyGlass. • Logic Equivalence Checks using cadence conformal. • Caliber checks at front end using Fusion compiler. • VCLP using VC static for UPF checks. • Fishtail flow for promoting IP level constraints to SoC. • RTL models and test benches using HDL. • SoC integration of IP\'s and shared component\'s. Knowledge of RTL integration, UPF flow, STA and synthesis.

Experience

1. Senior Rtl Design Engineer

   Wipro

   Nov 2024 — Present · Hyderabad, IN

   Client - Google

Education

• Shri Guru Gobind Singhji Institute of Engineering and Technology, Vishnupuri, Nanded

  Master of Technology, Electronics

  2013 — 2015

• Dr. D. Y. Patil Institute of Technology, Pimpri, Pune

  Bachelor of Engineering - BE, Electronics Engineering

• Centre for Development of Advanced Computing (C-DAC)

  PG Diploma, VLSI Design

Skills

• Management
• Research
• Leadership
• Project Management
• Microsoft Word
• Microsoft Office
• Microsoft Excel
• Powerpoint