Pranit Jannawar
Senior Pre Silicon System Validation Engineer at Intel
- Role
- System Validation Engineer at Intel
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
System Validation Engineer
Apr 2022 — Present
Education
Jawaharlal Nehru Technological University
Bachelor of Technology (B.Tech.), Electricals and Electronics Engineering
2008 — 2012
University of Minnesota
Master's degree, Electrical and Electronics Engineering
2012 — 2015
Harvard Business School Online
CORe Credential of Readiness, Business Administration and Management, General
2017 — 2018
Skills
- Logic Synthesis
- Physical Design
- Testing
- Microcontrollers
- Electronics
- Computer Architecture
- Matlab
- Circuit Design
- Verilog
- Electrical Engineering
- Vhdl
- Cadence
- Simulink
- Cadence Icfb
- Java
- Simulations
- Vlsi
- Cadence Virtuoso
- C++
- Asic
- C
- Integrated Circuit Design
- Pspice
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