Pranay Nandanwar
Lead Formal Verification
- Role
- Senior Staff Engineer at Samsung Semiconductor
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Pranay Nandanwar
Formal & Design Verification Engineer with 9+ years of experience, including 4+ years in Formal Verification. Expert in formal verification techniques, methodologies, and strong debug skills. Proven track record in end-to-end formal testbench development, SVA-based verification, and achieving high coverage closure.Worked on complex IP\'s and subsystem designs such as controllers, reliability flows, debug fabrics, and low-power subsystems—identifying critical bugs that led to design and security enhancements and prevented potential silicon respins.Skilled in Formal Property Verification(FPV), Design Verification (UVM), SystemVerilog, Verilog HDL, and protocols like AXI, SPI, I2C, I3C, and QEP, with expertise in formal abstraction techniques, coverage-driven sign-off, and team leadership.
Experience
Senior Staff Engineer
Sep 2025 — Present · Bengaluru, IN
Education
Yeshwantrao Chavan College of Engineering - YCCE
Master of Technology (M.Tech.), VLSI Design
2014 — 2016
S.B. Jain Institute of Technology,Management & Research, Nagpur
Bachelor of Engineering (B.E.), Electronics and Telecommunication Engineering
2009 — 2013
Skills
- Engineering
- System Verilog
- C
- Programming
- Verilog
- Electronics
- Matlab
- Rtl Design
- C++
- System Verilog
- Windows
- Universal Verification Methodology (Uvm)
- Rtl Verification
- Digital Electronics
- Microsoft Office
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.