Pranav Kachhwaha
- Role
- Design Verification Engineer at Microsoft
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Pranav Kachhwaha
ASIC Design & Verification
Experience
Design Verification Engineer
Mar 2016 — Present
Designing and co-managing combinational testing of the logic blocks of a HoloLens IC • Authoring and maintaining verification suites as verif owner for three digital blocks/components • Executing extensive pre-silicon and post-silicon testing, including bring-ups • Administering and running simulation regressions for two chips • Leading meetings with designers and test writers—offering, collaborating, and optimizing solutions • Composing Perl and bash scripts to enhance efficiency and automation in verification efforts
Education
Purdue University
Bachelor of Science - BS, Electrical Engineering
2004 — 2008
San José State University
Master of Science - MS, Electrical Engineering
2012 — 2017
San José State University
Computer Science
2010 — 2011
Brebeuf Jesuit Preparatory School
High School
Santa Clara University
Electrical Engineering
2009 — 2009
Skills
- Pcie
- Application-Specific Integrated Circuits (Asic)
- Bring-Up
- Eda
- Cadence
- Very-Large-Scale Integration (Vlsi)
- Verilog
- Rtl Design
- System Verilog
- Logic Design
- Tcl
- Soc
- Functional Verification
- Tapeout
- Asic
- C
- Perl
- Unix Shell Scripting
- Vhdl
- Physical Design
- Java
- Fpga
- Implementation
- Systemverilog
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