Pranav Nair
- Role
- Component Design Engineer at Intel
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
Experience
Component Design Engineer
Aug 2021 — Present · Bengaluru, IN
Leading DFT Execution at SS and SoC Level on Intel® FPGA product line - Handling DFT Architecture and test clocking, RTL Implementation (TAP/IJTAG/EDT/SSN/MBIST), Spyglass DFTDSM, SCAN Implementation, Test Constraints, ATPG and GLS.
Education
Indian Institute of Technology, Madras
Bachelor of Technology (B.Tech.), Master of Technology (M.Tech.), Electrical Engineering
2009 — 2014
Atomic Energy Junior College
Higher Secondary Certificate, Electronics
2007 — 2009
Atomic Energy Central School
Senior Secondary Certificate
2001 — 2007
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