Pranav Verma

About Pranav Verma

Vast experience of IP Verification and design. Have been working on load-store unit verification of next generation DSP core designs. Microarchitecture understanding of caches, memory organization, cache optimzation techniques.Managing a team of motivated design and verification engineers working on unit/block level design and verification of CPU/DSP architecture. Actively involved in all aspects of RTL verification from - Verification planning, Testbench infrastructure development including checkers, monitors, stimulus generators, functional coverage and debugging- Design and microarchitecture of Compression unit in the processor- RTL design and integration. Worked on RTL integration, with complete RTL development flows, CDC, Lint, etc- Expert in Processor Architecture- Familiar with most of RTL verification tools

Experience

1. Mts

   AMD

   Jan 2020 — Present

   Verification of Load Store Data Cache unit of ARM ISA based and X86 (dual ISA) processor.• High level testplan of various LSDC (load,store, data cache) Unit components for ARM based AMD’s next generation core. Coherency testplan at SOC level.• LS Monitor: Developed the LS unit aggregator which behaves like an instruction monitor and gives a relative age-order view of the instructions involving load/store operations with the respective instructions attributes. It collects the information from all the itnerfaces which interact with LS unit for checkers to query and for easier debug. Language – C++• Random Stimulus generator: Exclusive ops generator: ARM exclusive ops requestor for Atomics and Exclusives. Generated interesting cases with multi-threaded scenarios to uncover bugs with Exclusive load/store ops.• Checker: o Developed Store to load forwarding checker which checks for all the scenarios of STLF feature of LS unit. Language – C++o EndToEndChecker for Ordering checks for Device/Strongly Ordered memtypeso Exception Checker –To compare the RTL fault generation after the Page walk vs ExpectedFault for a particular load/store operation• Interface assertions:o LS-EX interface to capture the Load Store to Execute unit interface signal protocols – Language - SVo Interface assertions for LS-FP interface to capture the Load Store to Execute unit interface signal protocols – Language SV• Bringup: Features: EMEM (emulation memory), SRB (special registers read/write) bringup for LS unit verification, Exception (Faults/Page Faults), STLF(store-load forawrding).• Debug: Debugging various failures in LS unit regressions with features ranging from Paging, memory model mismatches, Exceptions, EMEM, SRBs, Stlf, etc.• Coverage: Coverage coding and closure for LSDC Unit verification in System Verilog.SOC/SubSystem:Subsystem level coherency testplanning, stimulus generation, coverage imports

Education

• Bvb

  Ssc

Skills

• Computer Architecture
• Rtl Coding
• Testing
• Processors
• C++
• C
• Systemverilog
• Digital Electronics
• Arm Architecture
• Assembly
• Vlsi
• Coverage Analysis
• Asic
• Digital Design
• Verilog
• Microprocessors
• Rtl Design
• Soc
• Simulation
• Functional Verification
• Debugging