Pranav Kothe
System-on-Chip Design Engineer at Intel Corporation
- Role
- System-on-chip Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Pranav Kothe
Senior Design Engineer with 4+ years of experience in VLSI Design domain having good knowledge and experience in developing RTL using Verilog and VHDL.• Hands on experience of block level as well as SOC level logical synthesis using Design compiler(synopsys) and Genus(Cadence).• Good experience of scripting languages like Perl for automation and to debug the issues faced. And also TCL for inserting ECO’s in the netlist using Design Compiler from Synopsys.• Hands on experience on some tools from Cadence like SimVision for simulation of RTL codes and LEC conformal for logical equivalence check.• Experience in FPGA implementation which also includes softcore processor, Microblaze.
Experience
System-on-chip Design Engineer
Oct 2020 — Present · Bengaluru, IN
Education
St. Vincent Pallotti College of Engineering & Technology
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering
2007 — 2011
Shri Ramdeobaba College of Engineering and Management
Master of Technology - MTech, VLSI Design
2011 — 2013
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.