Prakhyath Nagaraj

About Prakhyath Nagaraj

Focused on GPU/Compute IP-level PPA (Power, Performance, Area) analysis, driving gen-to-gen and competitive area benchmarking to guide architectural efficiency. Experienced in IP and cluster-level area estimation, tracking, and convergence across design milestones. Passionate about power debug and cdyn optimization, improving clock gating efficiency, and collaborating closely with EDA partners to brainstorm and implement innovative optimization techniques.

Experience

1. Senior Gpu Ppa Engineer - Area & Power

   Intel

   May 2025 — Present · Santa Clara, CA, US

   I specialize in driving GPU power and area efficiency through workload-driven optimization, early architecture-aware estimation and gen-to-gen PPA analysis.• Performed workload-driven power analysis using emulation activity to idnetify dynamic power hotspots and guide backend optimizations (Multibit Banking, Clock Gating, VT swapping, Clock Tree Optmization)• Collaborated with Synopsys AE teams to refine Fusion Compiler power optimization flows and improve backend PPA efficiency.• Led feature-level area estimation and convergence across GPU IPs, enabling early architecture configuration and floorplanning decisions.• Monitored implementation area trends, identifying hierarchy-level bottlenecks and escalating risks to microarchitecture teams

Education

• San Francisco State University

  Master of Science - MS, Electrical and Electronics Engineering - VLSI

• Visvesvaraya Technological University

  Bachelor's degree, Electrical, Electronics and Communications Engineering

  2016 — 2020