Prakhar Srivastava
Lead Verification Engineer
- Role
- Lead Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Prakhar Srivastava
I am a Design Verification Engineer with 7+ years of experience delivering first-pass…
Experience
Lead Design Engineer
Jan 2025 — Present · Noida, IN
DDR Memory Controller (Project 1)• Migrated legacy testbench to align with latest VIPs.• Ran regressions, debugged AXI interface issues, and worked with design teams to drive fixes.• Ensured compatibility with evolving protocol models while maintaining regression quality.DDR Memory Controller (Project 2)• Added assertions for new I/O ports, ensuring design intent correctness.• Expanded coverage with additional coverpoints for new parameters/signals and clock frequencies.• Reported missing design documentation to design teams, strengthening spec clarity.Key Achievements: Improved debug efficiency, enabling faster closure of AXI interface issues. Recognized for elevating verification maturity within a short span.
Education
ABES Engineering College
BTech - Bachelor of Technology, Electrical, Electronics and Communications Engineering
2014 — 2018
ABES Engineering College
Bachelor's degree, B.Tech (Electronics and Communication Engineering)
2014 — 2018
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