Prakash Thatigiri

Experience

1. Engineering Manager

   Intel

   Apr 2019 — Present

Skills

• Asic
• Processors
• Cmos
• Timing Closure
• Static Timing Analysis
• Rdl
• Primetime
• Dft
• Tcl
• Rtl Design
• Physical Design
• Floorplanning
• Logic Design
• Clock Tree Synthesis
• Mixed Signal
• Formal Verification
• Eda
• Systemverilog
• Verilog
• Logic Synthesis
• Low-Power Design
• Functional Verification
• Bump Planning
• Rtl Coding
• Redhawk
• Emir
• Physical Verification
• Integrated Circuit Design
• Microprocessors
• Cadence Virtuoso
• Vlsi
• Drc
• Soc
• Lvs
• Ic