Prakash Palanisamy
Staff Failure Analysis R&D Engineer / Pathfinding / Materials Scientist / Electron Microscopy at Intel Corporation
- Role
- Senior Staff Failure Analysis Circuit Edit R & d Engineer-pathfinding at Intel
- Location
- Beaverton, OR, US
- LinkedIn followers
- 500 followers
About Prakash Palanisamy
Experienced Materials Scientist with strong fundamentals and working experience in metals, semiconductors, ceramics, intermetallics, magnetic materials, metallic glasses.• Failure Analysis Expert. Defect investigation using SEM/TEM/Tomography.• Performed channel strain analysis using Nano-beam e-diffraction, Electron-Energy loss spectroscopy, Precession e-diffraction, In-situ electrical biasing in TEM for electro-migration, In-situ heating and cooling to study phase transformation, STEM tomography, HR-TEM of SiGe, GaN, GaAs.• Strong knowledge and experience with semiconductor device physics and manufacturing process such as thin film deposition using ALD, CVD, PVD and etch cleans, lithography, Metallization and semiconductor device testing. Proficient in Front-End, Back-End of Line process, Novel Interconnect Materials.• Proficient in materials characterization. Expert in imaging, chemical and structural characterization using TEM/STEM/EELS, DIB, SEM, XRD, DSC, TGA/DTA, SIMS analysis. Circuit Edit - Pathfinding. Tools and Methodology development for advanced technology nodes. Ne+/ He+/ Ga+ tools.• Excellent understanding of structure-processing-property correlation of Advanced Materials.• Strong knowledge in metallurgical processes and mechanical testing of materials.• Experience in Grain orientation analysis. Grain size-mechanical/electrical property correlation.• Fabricated small structures and TEM sample preparation using SEM-FIB/DIB.• Lean six-sigma green belt, proficient in design of experiments (DoE), statistical process control and utilization of statistic tools such as JMP.• Good teamwork and analytical capability; collaborated across multiple teams in Intel corp. Guided and contributed significantly for advanced materials development for components research and pathfinding.
Experience
Senior Staff Failure Analysis Circuit Edit R & d Engineer-pathfinding
Aug 2022 — Present · Santa Clara, CA, US
Advanced methodology development for Circuit Edit. Tools / Materials / Characterization.
Education
Government College of Engineering, Salem
Bachelor of Engineering, Metallurgical Engineering
1999 — 2002
Devanga High school
High school
Sree Narayana Guru Institute of Technology Coimbatore
Diploma of Education, Mechanical Engineering
Indian Institute of Science (IISc)
Masters in Engineering, Metallurgical Engineering
2002 — 2004
University of Virginia
PhD, Materials Science and Engineering
2008 — 2011
Skills
- Xrd
- Metallurgy
- Experimentation
- Design of Experiments
- Tem
- Materials Science
- Powder X-Ray Diffraction
- Scanning Electron Microscopy
- Characterization
- Spectroscopy
- X-Ray
- Sem
- Sputtering
- Nanotechnology
- Materials
- Mechanical Testing
- Fib
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