Prakash Narayanan

About Prakash Narayanan

DFT Manager responsible for DFT design, verification, post-silicon bring-up and enabling RTP of the product.1. Hands-on knowledge on different ATPG tools - Mentor TestKompress/Fastscan, Synopsys Tetramax, Cadence Encounter Test.2. Memory BIST3. DFT RTL for test controller, JTAG, test clocking, etc.4. Boundary Scan5. Hands-on silicon bring-up knowledge in different tester platforms - TI Internal, Teradyne and Advantest.6. Publications and patents across various different aspects of DFT - ATPG, Boundary Scan, Memory Test, Self-Test solutions, etc.

Experience

1. Dft

   Google

   Jul 2021 — Present · Bengaluru, IN

Education

• Arizona State University

  MSE, Electrical Engineering

  2000 — 2002

• Sri Venkateswara College of Engineering or SVCE

  Bachelor of Engineering (B.E.), Electronics and Communications

  1996 — 2000

Skills

• Ic
• Rtl Coding
• Asic
• Mixed Signal
• Dft
• Soc
• Physical Design
• Eda
• Rtl Design
• Cmos
• Verilog
• Static Timing Analysis
• Functional Verification
• Timing Closure
• Ncsim
• Atpg
• Vlsi
• Low-Power Design