Prajwal M G
- Role
- Soc Design Engineer at Intel
- Location
- Hillsboro, OR, US
- LinkedIn followers
- 500 followers
Experience
Soc Design Engineer
Feb 2022 — Present
Working on 5nm node using fusion computer to run APR runs on partition. Running the PV tools on the Partition to check on Antenna, DRC and LVS errors. FEV VCLP
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