Raghavendra R

About Raghavendra R

Engineering professional with 18+yrs of experience in ASIC Design Verification methodologydevelopment and deployment- Involved in building the teams, managing cross functional teams, globally distributed teams and facilitate verification activities such as functional model, directed and constrained random test development to achieve coverage metrics- Experience in full chip/IP test bench development, integration of third-party VIP’s, SOC functionalverification, Gate-level bring up & debug- Working Knowledge on Microcontrollers, Slimbus, DSI, AMBA, uBL, high/low speed peripherals,SDIO, FuSa(Functional Safety), PA(Power-Aware)sims, flash memory, CCU, PMU and MBIST controllers- Languages/Methodology: C, C++, UVM, SV, SVA, RAL models, Assembly; Scripting: Perl, basic python- Managed and lead pre-silicon verification of IP, subsystem & SOC\'s from resource planning, development plan and successful execution of the projects.

Experience

1. Principal Soc Verification Engineer

   Microsoft

   Jan 2026 — Present · Bengaluru, IN

Education

• Ratnam Junior College, Nellore

  Intermediate, MPC

  1999 — 2001

• Saradha vidhya Nilayam

  10th Class, High School/Secondary Certificate Programs

  1998 — 1999

• Jawaharlal Nehru Technological University

  Bachelor of Technology (BTech), ECE

  2002 — 2006

Skills

• Verilog
• Asic
• Systemverilog
• Soc
• Vlsi
• Formal Verification
• Eda
• Open Verification Methodology
• Specman
• Perl
• Cadence
• Firmware
• C
• C++
• Functional Verification
• Rtl Design
• Ncsim
• Static Timing Analysis
• Vhdl
• Modelsim
• Tcl
• Rtl Coding
• Application-Specific Integrated Circuits (Asic)
• Very-Large-Scale Integration (Vlsi)
• System on a Chip (Soc)
• Semiconductor Industry
• Silicon
• Semiconductors