Prafulla Palaskar
Principal Design engineer at Cadence Design System
- Role
- Principal Design Engineer at Cadence
- Location
- Pune, MH, IN
- LinkedIn followers
- 500 followers
About Prafulla Palaskar
Certified Functional Safety Professional with 8 years of experience in Verification of Automotive DSP IPs.Responsible for collection of Verification Evidences for Safety Analysis and Audits. Contributed to the development and verification of various Hardware as well as Software Safety mechanisms to achieve targeted ASIL levels. Lead the team towards timely and high quality delivery of customers\' Functional Safety Products.
Experience
Principal Design Engineer
Jul 2022 — Present · Pune, IN
Development and Verification of Software tests (runtime and reset-time) library to find faults in hardware in actual vehicle- Functional Safety Certification of STLs
Education
Government Polytechnic Nashik
Diploma, E&TC
2009 — 2012
Vishwakarma Institute Of Technology
Bachelor of Technology - BTech, E&TC
2012 — 2015
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