Prafulla Gaikwad

About Prafulla Gaikwad

A highly motivated and enthusiastic physical design engineering manager with over 19 years of experience in ASIC backend.Proven silicon experience with multiple tape outs of multimillion gates, high speed, low power and complex chips with varying process nodes from 110nm to 5nm.Extensive experience in fullchip STA lead role and as an individual contributor timing engineerExperience in synthesis and SOC constraint development & validation. Experience in writing DDR interface constraints(SDRAM and ONFI) and hands on experience in timing closure of critical DDR interfaces.Very proficient in all stages of ASIC physical design including Floorplan, Placement, CTS, Optimization, Routing, Timing Closure, Crosstalk analysis, Electrical fixes, Eco cycles and Physical closure.Experience in fullchip floorplanning, block level timing budgets, fullchip clock tree balancing.Experience in leading team of engineers for Synthesis, P&R and STA closure.Hands on work experience in writing manual timing ECO and STA closure. Experience in evaluating CAD tools, training PD engineers on tools, flow and methodology.Experience in driving PPA attainment for high speed graphics designExperience in people management, project planning, schedule, recruitment and hiring decision Proficient in using EDA tools of Synopsys and CadenceSpecialty: Synthesis, STA, physical design, PPA attainment

Experience

1. Principal Engineer

   AMD

   Jun 2018 — Present · Orlando, FL, US

Education

• Indian Institute of Technology, Bombay

  Master of Technology (M.Tech.), Microelectronics

  2001 — 2003

Skills

• Tcl
• Rtl Design
• Timing Closure
• Asic
• First Encounter
• System on a Chip (Soc)
• Vlsi
• Parasitic Extraction
• Lvs
• P&R
• Ic
• Ptsi
• Very-Large-Scale Integration (Vlsi)
• Logic Synthesis
• Application-Specific Integrated Circuits (Asic)
• Physical Verification
• Equivalence Checking
• Clock Tree Synthesis
• Nanoroute
• Processors
• Verilog
• Floorplanning
• Physical Design
• Soc
• Static Timing Analysis
• Synopsys Tools
• Primetime
• Conformal Lec
• Star-Rcxt
• Eda
• Flow Development