Prafull Jain
Design Verification Engineer at (IBM - ISDL)
- Role
- Design Verification Engineer at Ibm India System Development Lab at IBM
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Prafull Jain
Proficient with verification using UVM, Verilog, System Verilog. Worked on IP and subsystem level verification. Protocol expertise with APB, AXI, AHB, JTAG and Nvme Protocol. Scripting languages known Perl and python. Exposure to Assertion. Hands on experience with test planning, test coding, functional coverage creation, closure, code coverage analysis.
Experience
Design Verification Engineer at Ibm India System Development Lab
Mar 2025 — Present · Bengaluru, IN
Education
IET DAVV INDORE
Bachelor of Engineering, Electrical, Electronics and Communications Engineering
2014 — 2018
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