Pradyumna Katageri
Design Verification Engineer @Accenture (ATCI).
- Role
- Senior Silicon Engineering Analyst at Accenture
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Pradyumna Katageri
Sub-Sytem Integration level Design Verification Engineer and a Pythoneer with 5+ years of…
Experience
Senior Silicon Engineering Analyst
Feb 2025 — Present
Integration-level verification for a BIST insertion IP designed to validate data flow across the CHI bridge connecting two power domains. Developed and executed tests using a SystemVerilog-UVM testbench to ensure functionality and robustness. Identified and reported two critical bugs across multiple projects, improving IP integration reliability. Formal verification owner of connectivity checks using Synposys VC Formal tool & using TCL scripting to check for critical signals throughout the ARM Cortex X925 core design based on their description given in the integration specification and using it to improve toggle coverage by 9.5%. Perfomed UPF power aware verification for the core using a C test to program the internal power state controller to verify the expected voltages on the power switches inside the core.
Education
Sir M Visvesvaraya Institute Of Technology
Bachelor of Engineering, Electronics and Communication Engineering
2016 — 2020
Scaler
Data Science and Machine Learning
2022 — 2023
Vasantrao Naik Mahavidyalaya
12th Science
Sir M Visvesvaraya Institute Of Technology
Bachelor's Degree
Ryan International School
10th
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