Pradeep Padmanabhan
principal Design Engineer at Cadence Design Systems
- Role
- Principal Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Principal Design Engineer
Jul 2024 — Present · Bengaluru, IN
Education
ST.FRANCIS INTEGRATED HIGH SCHOOL VENKATAGIRI
Schooling
1994 — 2006
National Institute of Technology, Tiruchirappalli
Master’s Degree, VLSI SYSTEMS
2013 — 2015
Narayana Engineering College Gudur F1
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering
Skills
- Floorplanning
- Verilog
- System Verilog
- Joint Test Action Group (Jtag)
- Modelsim
- Electronics
- Tdf
- Cadence Virtuoso
- Manufacturing
- Synopsys Primetime
- Fpga
- Mbist
- Boundary Scan
- Scan Insertion
- Asic
- Crm
- Dft
- C
- Programming
- Axi
- Rtl Verification
- Xilinx Ise
- Validation
- Uvm
- Emulation
- Static Timing Analysis
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