Prabul Kanth P M
IP Integration & Validation Engineer at Intel Corporation
- Role
- Ip Integration & Validation at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Prabul Kanth P M
RTL Design professional, Experience is SoC Integration, Subsystem Integration, DRC checks…
Experience
Ip Integration & Validation
Sep 2020 — Present · Bengaluru, IN
Education
SANDEEPANI SCHOOL OF VLSI DESIGN
PG DIPLOMA IN VLSI DESIGN (FPGA Based), VLSI Design, FPGA,Verilog
2008 — 2009
AMRITA SCHOOL OF ENGINEERING
B.Tech, Electronics and Communication
2003 — 2007
SAINIK SCHOOL KAZHAKOOTAM
Schooling, Science;,Maths, Social Science, English, Malayalam
1996 — 2003
Skills
- Rtl Design
- Rtl Coding
- Semiconductors
- Fpga
- Vhdl
- C++
- Embedded Systems
- Eda
- Altera
- Modelsim
- Altera Quartus
- Xilinx
- Chipscope Pro
- Verilog
- Edk
- Xilinx Ise
- Rtl Development
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