Pouya Taatizadeh

About Pouya Taatizadeh

Industrial and academic experience in design and verification of large-scale high-speed ASICs.Interests- Design of high performance SoCs from specification - Assertion-based Verification and Validation- Formal Verification- FPGA-based emulation platforms for functional verification/validation- Developing generic and automated methodologies for verification reuse. Skills- PROGRAMMING: C, C++, Python, Bash, TCl- HDL/HVL: Verilog, System Verilog, SVA assertions, UVM, VMM, VHDL -TOOLS: Cadence Incisive IRUN, Synopsys VCS, Incisive Formal Verifier, VManager, IMC, Design Compiler, Questasim -OTHER: Unix, SVN, Perforce, Jira, LaTeX, XML

Experience

1. Design Verification Engineer

   Meta

   Apr 2024 — Present · San Francisco, CA, US

   Silicon Infra Custom ML/AI ASIC Chips

Education

• University of Southampton

  Master of Science (M.Sc.), System-on-Chip

  2010 — 2011

• University of Southampton

  Bachelor of Engineering (B.Eng.), Electronic Engineering

  2007 — 2010

• McMaster University

  Doctor of Philosophy (Ph.D.), Electrical and Computer Engineering

  2011 — 2016

Skills

• Spice
• System Level Design
• Cmos
• Matlab
• Very-Large-Scale Integration (Vlsi)
• Electronic System Design
• C++
• Python
• Latex
• Simulations
• C
• Programming
• Vlsi
• Systemverilog
• Digital Electronics
• Cadence Virtuoso
• Cad
• Algorithms
• Embedded Systems
• Eda
• Fpga
• Asic
• Verilog
• Field-Programmable Gate Arrays (Fpga)
• Integrated Circuit Design
• Microprocessors
• Rtl Design
• Soc
• Universal Verification Methodology (Uvm)
• Modelsim
• Functional Verification