Pouya Ashtiani
Fellow @AMD
North Vancouver, BC, CA
EMAILS
MOBILE NUMBERS
+91 *********19
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WORK HISTORY
Jul 2025 — Present
Fellow @AMD
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Vancouver, BC, CA
EDUCATION
2003 — 2007
University of Toronto
Masters of Engineering, Electrical
1997 — 2003
University of Toronto
Bachelor’s Degree, Computer Engineering
SKILLS
VerilogDebuggingLogic SynthesisComputer ArchitectureApi DevelopmentPythonTiming ClosureSystem on a Chip (Soc)Voltage RegulatorSerdesCadence VirtuosoDisplayport AuxMipiEdaSimulationsDisplayportPhysical DesignSiliconCircuit DesignIntegrated Circuit DesignAsicFunctional VerificationCustom DesignDftLow-Power DesignLow Level ProgrammingIcCmosVlsiPower AnalysisDesignsSystemverilogCEmbedded SystemsPllHardware ArchitectureFirmwareStatic Timing AnalysisPcieRtl Design
ABOUT POUYA ASHTIANI
Memory PHY Architecture
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