Poulomi Pal
Design Verification Engineer at Intel Corporation
- Role
- Design Verification Engineer at Intel
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Design Verification Engineer
Jun 2011 — Present
Education
North Carolina State University
MS- Thesis, Computer Engineering
2007 — 2009
RV College Of Engineering
B.E., Electronics and Communicaton Engg.
2002 — 2006
Skills
- Algorithms
- Software Engineering
- Tcl
- Matlab
- Debugging
- Operating Systems
- Embedded Software
- Rtos
- Asic
- Linux Kernel
- Linux
- Assembly
- Device Drivers
- Testing
- Windows
- Vhdl
- C++
- Eclipse
- Shell Scripting
- Unix
- Computer Architecture
- Architecture
- Verilog
- Perl
- Embedded Systems
- C
- Programming
- Optimization
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