Pooja T C

About Pooja T C

Hardware Design engineer with 3 years of experience highly proficient in microprocessor-based board designs, including interfacing with common peripherals (USB, UART, Ethernet) and serial communication protocols (I2C, SPI, I2S). Expertise in ESD design practices and testing, along with board bring-up and debugging utilizing tools like logic analyzers and digital oscilloscopes.Key Responsibilities:Capture and define system requirements and specifications.Select and procure components based on technical requirements, cost-effectiveness, and availability. Skilled in requirements capture, hardware specification documentation, and detailed schematic reviews.Proficient in preparing hardware requirements, hardware design documentation, and test plans, ensuring clear specifications, thorough design validation, and systematic testing procedures.Develop component symbols for ICs and discrete components using Cadence (ORCAD), Altium and Mentor Graphics XDX Designer.Design efficient schematics using Cadence (ORCAD), Altium and Mentor Graphics XDX Designer.Perform netlist creation, verify netlist integrity, and ensure accurate Bill of Materials (BOM).Experienced in layout activities including footprint and Layout creation, Gerber file generation, and CAM verification to ensure design integrity and manufacturability.Provide support for Signal Integrity (SI), Power Integrity (PI), and thermal analysis; capable of performing SI for high-speed signal designs.Expertise in power management circuit design and debugging.Generate and maintain requirement documents, design specifications, and board-related documentation.Develop and enforce layout guidelines, providing guidance to layout engineers.Perform comprehensive checks on board files, Gerber files, and DFM (Design for Manufacturability) analysis.Lead board bring-up and execute Engineering Development Validation Testing (EDVT) in collaboration with software teams.In-depth experience in debugging board issues using logic analyzers and high-end oscilloscopes.Ensure compliance with EMI/EMC guidelines and testing requirements. Responsible for power supply design, DFM, and DFT (Design for Testability) considerations.Proven ability to provide ongoing sustenance support and perform product qualifications.Experience in leading and managing teams throughout the entire product development lifecycle.

Experience

1. Lead Engineer

   HCLTech

   Sep 2022 — Present · Bengaluru, IN

   Skilled in Aircraft braking controller system Re-design and analysis tolerance analysis, worst case simulations, Redesign activity, Power supply design, Project proposal preparation, training young engineers.Skilled in Re-design of Aircraft waste management system and linear motion system, analysis & inspection test procedure preparation, simulations, tolerance analysis, worst case simulations, Redesign activity, filter design, Power supply design.Aircraft power and sensing, system, Aircraft Gas Turbine and Fuel System.

Education

• Siddaganga Institute of Technology, Tumakuru (SIT Tumkur)

  Bachelor of Engineering - BE

  2019 — 2022

• Siddaganga polytechnic

  Diploma in electronics and communication engineering

  2016 — 2019