Pooja Sakri

About Pooja Sakri

Overall experience of 10+ years in Physical Design Experienced in handling complex blocks in terms of timing, power, utilization, routing congestion etcHave excelled in various tapeouts in Tile HMs (SOC NOC HMs) as PD implementation lead including closure of all signoff activitiesWorked on various projects in 10nm, 8LPE,5LPE, 4nm tech nodesExperienced in leading a new team of 4-5 members and delivered 7-8 blocks across multiple projects which has various challenges and complexities (FT dominated, critical timing interfaces, high utilization, power hungry, CTS closure critical, congestion critical, floorplan challenges, multi voltage and power domains)Hand on experience with different tools like Innovus, ICC2, FCSome experience in physical verification (Fxiing of DRC, Antenna, ERC, Softcheck, DPM violations)Experience in fixing power distribution network violations (secondary power resistance,Loop resistance violations, Dynamic/Static IR)Willingness to learn about new technologies, new skills and improve skills

Experience

1. Staff Engineer

   Qualcomm

   Dec 2024 — Present

Education

• Manipal Institute of Technology

  Master of Technology (MTech), Microelectronics

  2012 — 2014

• Basaveshwar Engineering College

  Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering

  2007 — 2011

Skills

• Physical Design
• Cadence Virtuoso
• Semiconductors
• Mixed Signal
• Electronics
• Microcontrollers
• Plc
• Analog Circuit Design
• Asic
• Verilog
• Perl
• Embedded Systems
• Eda
• C
• Soc
• Integrated Circuit Design
• Methodology
• Digital Electronics
• Vlsi