Pooja Raghav
ASIC Design Engineer at Synaptics | Ex-FPGA Design and Verification at AMD | Ex-Intel | M.Tech’24 (VLSI) NIT Delhi
- Role
- Asic Design Engineer at 新思國際科技有限公司
- Location
- Ghaziabad, UP, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Asic Design Engineer
Jul 2025 — Present · Bengaluru, IN
Education
National Institute of Technology Delhi
Master of Technology - MTech, VLSI
2022 — 2024
Inderprastha Engineering College
Bachelor of Technology - BTech, Electronics and communication
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