Pooja Agarwal
SRAM Design | Google | Samsung | ARM
- Role
- Circuit Design Engineer,silicon at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Pooja Agarwal
I may be described as an avid and perpetual learner.I have experience in bitcell Analysis, leakage & PPA optimization, Read & Write Margins, Assist circuits and Compiler Integration.I also like solving mathematical and analytical questions.Besides this, I occasionally indulge myself in reading and playing badminton. I believe nothing is enough ever so I require to learn a lot in comparatively lesser time.
Experience
Circuit Design Engineer,silicon
Oct 2024 — Present · Bengaluru, IN
Education
Indian Institute of Technology, Delhi
Master of Technology - MTech, Integrated Circuit Design
2018 — 2021
Dr. v.s.e.c,kidwai nagar,kanpur
High School
2006 — 2010
Hansraj college/delhi iuniversity
Bsc (Hons), Electronics
2010 — 2013
Delhi University
Msc, Electronics
2013 — 2015
Skills
- Windows
- Management
- Powerpoint
- Microsoft Excel
- Public Speaking
- Microsoft Office
- Programming
- Matlab
- Microsoft Word
- Vhdl
- Teamwork
- C++
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