Kishan P
Senior Principal Design Engineer at Cadence Design Systems
- Role
- Senior Principal Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Kishan P
Verification Engineer with hands on experience in System Verilog - UVM based IP and SoC Verification, with extensive experience in 3rd party VIP Integration and Bring-up. Also worked on XPROP Simulation, Gate Level Simulation and Low Power Simulation with CPF. Have good understanding of protocols like PCIe Gen4/5, AXI4, I2C and APB.
Experience
Senior Principal Design Engineer
Jan 2026 — Present · Bengaluru, IN
Education
GHS Markanja
Secondary Education, High School/Secondary Certificate Programs
2006 — 2009
Vivekananda Pre University College Puttur
Pre-University Education, PCME
2009 — 2011
JSS Academy Of Technical Education Bangalore
Bachelor of Engineering (BEng), Electronics and Communications Engineering
2011 — 2015
Skills
- Functional Verification
- Microsoft Excel
- Red Hat Linux
- Basic C
- Microsoft Office
- Microsoft Word
- Synopsys Certitude
- Ncsim
- System Verilog
- System on a Chip (Soc)
- Gate Level Simulation
- Matlab
- Mentor Graphics Questa
- Shell Scripting
- Uvm
- Perl
- Code Composer Studio
- Synopsys Vc Static
- Linux
- Verilog
- Pspice
- C++
- Cadence Insiciv
- Synopsys Vcs
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.