Pj Nicholas

About Pj Nicholas

Top-performing engineering professional with a track record of: innovation, first-time product success, on-time delivery, isolating and resolving complex silicon issues. Over 20 years of experience in custom I/O mixed signal, circuit and layout design. Effective team leader with hands-on experience in library and software coordination.Areas of exceptional strength:>>IO Design Engineer-Completed pre to post layout design using computer aided schematic capture, simulation and verification tools. Guided layout engineers for optimal device placement and routing to reduce parasitic effects on design-ASIC I/O Architectures – LVCMOS, I2C, MDIO, ONFI, and DDR interfaces-Designed level translator used in all I/Os; focusing on performance, DC power and area. Enhanced design in 16nm reduced DC power by 400%, area by 30% with no loss in performance vs. 28nm-Lead engineer for designs migrating to new technology. Collaborated with technology team to validate early model’s accuracy and evaluate device parameters based on I/O needs. Advised technology team on requests to the fabrication vendor for modifications to the process.>>Standard Cell Library Lead -Oversaw design, layout, deployment and communicated schedules and deliverables of standard cell libraries-Responsible for gathering and processing business units’ custom cell requests, providing design reviews and support-Wrote and executed quality control checks for integration at chip level.>>Physical Design-Physical layout of analog and mixed signal IC circuits-Wrote SKILL code to streamline metal fill pattern routine increasing layout team’s productivity and trained others in its use.Highlights of technical experience-IO Mixed signal design-Software Scripting-Team Player and Leader-Layout Verification Tools-Patents: 8,373,441 – Orienting Voltage Translators in Input/Output Buffers, 20138,536,925 – Voltage Level Translator Circuit, 20138,362,803 – Mode Latching Buffer Circuit, 2013

Experience

1. Staff Engineer

   Broadcom

   Aug 2000 — Present

Education

• Lehigh University

  M.S.E.E.

  2001 — 2004

• Penn State University

  B.S.E.E

  1995 — 2000

Skills

• Asic
• Digital
• Semiconductors
• Analog
• Application-Specific Integrated Circuits (Asic)
• Synchronicity
• Cad
• Place and Route
• Soc
• Signal Integrity
• Perl
• Timing Closure
• Cadence
• Skill
• Physical Design