Manojna Pichikala

About Manojna Pichikala

As a Masters Student in Computer Engineering at Oregon State University, I am expanding my knowledge and skills in computer architecture, machine learning, and embedded systems. I have also earned multiple Cadence certifications in SystemVerilog Assertions, Accelerated Verification with UVM and Jasper Formal Verification Fundamentals demonstrating my proficiency and expertise in verification methodologies and tools. My goal is to apply my knowledge and experience to design and verify cutting-edge and complex ASICs for various applications and domains.I have a strong background in image processing algorithms, pixel-level interfaces, and hardware description languages, such as VHDL, SystemVerilog, and UVM. I leveraged these skills to create accurate and efficient verification test-benches, test sequences, and test scripts for an Image Sensors processor ASIC at onsemi, ensuring high-quality and reliable performance. I also have experience in machine learning, as I worked on a project to predict soil water tension in vineyards using LTSM and ARIMA models at AgAID Institute. I am passionate about learning new technologies and solving challenging problems in the field of digital design and verification.

Experience

1. Electrical Engineer

   Caltrans

   Oct 2023 — Present · CA, US

   Performing traffic engineering and traffic management analysis to monitor and recommend regional integration of ITS operations by analyzing the Ramp Metering Information systems (RMIS) database.• Preparing plans, specifications, and estimates for the design of ITS and TMS including inspection of ITS hardware

Education

• R.V.R. & J.C. College of Engineering

  Bachelor of Technology - BTech, Electronics and Communications Engineering

  2016 — 2020

• Oregon State University

  Masters, Computer Engineering