Bablu Mukherjee

Micron Technology | NAND Design Rule | Process Integration | Advanced NAND Technology

Role
Senior Engineer - Nand Design Rule at Micron Technology
Location
Hyderabad, TG, IN
LinkedIn followers
500 followers

About Bablu Mukherjee

Electrical and material science engineer with a skill set in developing sensors, memory and low dimensional materials based devices. Having more than 10 years of experience in academics and industry R&D projects after receiving a Ph.D. degree.Professional with expertise in the field of 3D NAND memory as a semiconductor design rule engineer, specifically in NAND integration and memory technology development. Interest in contributing product improvements, new product introduction, cost reduction, speed increase and yield improvement in memory and storage company. I value collaboration, innovation, building competencies and excellence.# Knowledge of advanced process technology nodes including design rules and layout verification flows for production as well as R&D designs.# Failure Mode and Effects Analysis (FMEA) during design and provide new design solutions for designing for manufacturing (DFM) issues including Latch-up, ESD as well as process related failures (PFA, EFA) from PID, DE, CMP, DF.# Project management of new technology node introduction for new memory design collaborating with process integration, OPC, design, scribe, yield analysis teams.

Experience

  1. Senior Engineer - Nand Design Rule

    Micron Technology

    Aug 2022 — Present · Hyderabad, IN

    Advanced NAND Technology TeamR & D NAND Design Rule/Process Integration EngineerNAND Design Responsibilities# Responsible for NAND design rules and clean sheets.# Worked closely with PI, photo, reticle, Design, and PE teams to define future technology nodes for all designs to reduce the number of reticles tapped out per design.Reticle Creation and Verification# Responsible for various steps involved in reticle creation for CMOS, Array, interconnect, and BEOL layers across NAND technology nodes in both R&D and Production.# Involved in the definition, implementation, and verification of the CMOS and array.Troubleshooting and Yield Improvement# Heavily involved in troubleshooting various fab issues, especially layout-sensitive designs and yield loss-related design fixes.# Created standalone DRCs to catch failing locations with the Design team and help increase yield with the YE team.Simulation and Validation# Responsible for requesting TCAD, structure, OPC, electrical, and Reliability simulations for Die database design edit requirements.# Debugged test structure fail modes, including design rules validation and layout analysis to match specifications-Team co-ordination:# Co-ordinate the work of experienced engineers from Process Integration, Advanced Mask Design, Scribe & Frame, and Layout & Design to help direct development efforts for a new 3D NAND generation from early development until manufacturing ceasesProject responsibilities:# Assure that the right DRC’s (Design Rule Checks) are in place, assure appropriate reaction to deviation from established design rules# Work with Yield Enhancement, Product Engineers, Defect analysis, Param, and Quality Assurance teams to understand process issues related to the database layout, and prioritize development of solutions with Process Integration, Advanced Mask Design# Help design and evaluate test structures to provide data for next generation devices, to quantify process margin on current devices

Education

  • National University of Singapore

    Ph.D, Engineering Physics/Applied Physics

  • Indian Institute of Technology, Madras

    Master of Science - M.S., Physics

    2007 — 2009

  • Ramakrishna Mission Residential College

    Bachelor of Science - B.S., Physics

    2004 — 2007

Skills

  • Microscopy
  • Nanofabrication
  • Nanowires
  • Tem
  • Afm
  • Sem
  • Optical Microscopy
  • Nanoparticles
  • Research
  • Powder X-Ray Diffraction
  • Sensors
  • Materials Science
  • Electron Microscopy
  • Mathematical Modeling
  • Xps
  • Mathematica
  • Optoelectronics
  • Simulations
  • Thin Films
  • Nanomaterials
  • Photolithography
  • Semiconductor Device
  • Optics
  • Cvd
  • Experimentation
  • Experimental Physics
  • Nanotechnology
  • Microfabrication
  • Scanning Electron Microscopy
  • Materials
  • Matlab
  • Science
  • Labview
  • Characterization
  • Physics
  • Spectroscopy

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Bablu Mukherjee — Senior Engineer - Nand Design Rule at Micron Technology in Hyderabad, TG, IN | Unifers