Hemanth Patnala

About Hemanth Patnala

Over 17 years of experience with ASIC development and verification.• Creating and executing comprehensive verification plans and test plans for various IP blocks, subsystems, and SoCs, including coverage metrics.• Exceptional knowledge in creating SV/UVM verification environments, which are highly reusable and configurable for various stages of verification.• Developing system level use-case testing and performance testing.• Experience with Power-aware testing.• Hands-on knowledge with Assertion based verification recently started working with formal verification.• Domain knowledge in cellular baseband SoCs, ARM subsystem, Peripheral subsystems, Power and clock control logic

Experience

1. Principal Engineer

   高通

   Jan 2022 — Present · San Francisco, CA, US

Education

• Jawaharlal Nehru Technological University

  MS, VLSI Engineering

  2005 — 2007

• Andhra University

  BE, Electronics and Communications

  2001 — 2005

Skills

• Uvm
• Timing Closure
• Functional Verification
• Open Verification Methodology
• Internet of Things
• Gsm
• Rtl Design
• Tcl
• Asic
• Rtl Coding
• Soc Verification
• Power Aware Verification
• Very-Large-Scale Integration (Vlsi)
• Static Timing Analysis
• Assembly Language
• Systemverilog
• C++
• Specman
• Semiconductors
• System on a Chip (Soc)
• Application-Specific Integrated Circuits (Asic)
• Test Planning
• C
• Vlsi
• Vmm
• Primetime
• Physical Design
• M2m
• Field-Programmable Gate Arrays (Fpga)
• Low-Power Design
• Logic Synthesis
• Formal Verification
• Ncsim
• Soc
• Debugging
• Perl
• Verilog
• Amba Ahb