Phanindra Santhosh Vadrevu
Senior Verification Engineer @Arm
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WORK HISTORY
Senior Verification Engineer @Arm
Cambridge, GB
EDUCATION
Raghu Institute of Technology - India
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering
ABOUT PHANINDRA SANTHOSH VADREVU
Strong background in SystemVerilog and UVM-based functional verification, specializing in IP and SoC-level validation. Skilled in Audio Subsystem Verification, including ANC IP DV, and end-to-end verification of QCT System Timer IP, TSENS, Watchdog, and Clock Calibration.Functional verification of DFD components such as TAP2SB, VAD (Vendor Authorized Debug), SBB (Secure Boot Block), and security checkers. Well-versed in security controller verification at the core level and knowledgeable in QFPROM and IOMUX.Extensive experience in DFX validation, covering JTAG, TAP, SCAN, UBPC, SMP, and PVT,Proficient in industry-standard protocols, including AHB, JTAG2AXI, GPIO, SPI, I2C, and UART. Hands-on experience with UPF and GLS simulations, including SDFMAX/MIN corner-based GLS environment setup. Strong expertise in functional and code coverage assessmentCapable of analyzing Hardware Description Documents (HDD) to identify critical features and developing detailed test plans. Skilled in Perl scripting, Python scripting and Linux-based workflows, optimizing verification processes through automation and efficiency improvements.
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