Phanindra Eranki

About Phanindra Eranki

Strong foothold in ASIC Design/Verification and Test Environment creation using Verilog HDL, Specman/System Verilog and well versed with Cadence/Questasim/VCs simulation tools. Hands on experience of creating verification environment using OVM and eRM methodologies.Profound Knowledge on USB 2.0 EHCI Specification, JEDEC DDR 1/2/3/4 Specification, Industry standard bus protocols AHB, AXI and APB.Worked on verification of variety of DDR Controllers used in different applications i.e, Network processing, Streaming Video, MFP at various levels of ASIC Design Flow.Worked on Verification of Cortex R5 series based subsystem used in different Network Switch Engines.

Experience

1. Principal

   Broadcom

   Mar 2016 — Present

Education

• National Institute of Technology Warangal

  MTech, VLSI System Design

  2003 — 2005

Skills

• Soc
• Logic Design
• Uvm
• Rtl Verification
• Pcie
• Ddr
• Specman
• Rtl Coding
• Dft
• Cadence Virtuoso
• Physical Design
• Amba Ahb
• Verilog
• Low-Power Design
• Mixed Signal
• Arm
• Rtl Design
• Axi
• Eda
• Debugging
• Logic Synthesis
• Vlsi
• Tcl
• Xilinx
• Systemverilog
• Atpg
• Static Timing Analysis
• Functional Verification
• Open Verification Methodology
• Systemc
• Serdes
• Usb
• Fpga
• Asic
• Integrated Circuit Design
• Vhdl
• Simulations
• Timing Closure
• Hardware Architecture
• Formal Verification