Phanindra Edukulla

Senior Physical Design Engineer at Qualcomm | BITS Pilani

Role
Senior Physical Design Engineer at 高通
Location
Hyderabad, TG, IN
LinkedIn followers
500 followers

About Phanindra Edukulla

Interested in Digital Electronics and VLSI Design.

Experience

  1. Senior Physical Design Engineer

    高通

    Dec 2023 — Present · Bengaluru, IN

Education

  • JNTUH College of Engineering Jagityala

    Bachelor of Technology - BTech

    2015 — 2019

  • Birla Institute of Technology and Science, Pilani

    Master of Technology - MTech

    2021 — 2023

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Phanindra Edukulla — Senior Physical Design Engineer at 高通 in Hyderabad, TG, IN | Unifers